Logical Surveyor

Authors

  • Roberto Valentín Davis-Martínez Empresa Eléctrica Provincial Santiago de Cuba

Keywords:

TTL, Hardware, Boolean Logical, VHDL

Abstract

The compulogical mathematician designed with integrated circuits TTL has as intention to develop the abilities in practice of laboratory using an economic hardware dedicated to the students on junior and high school to familiarize him with the Booleana Logical so that they can science riddles in interactive form and offering the possibility of new designs of the logical cable. The old layout pattern was tested with software as OrCAD VHDL

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Published

2016-11-14

How to Cite

(2016). Logical Surveyor. Maestro Y Sociedad, 3(2). Retrieved from https://maestroysociedad.uo.edu.cu/index.php/MyS/article/view/1759

Issue

Vol. 3 No. 2 (2006)

Section

Artículos

License

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